Multi-stage analog-to-digital converters (ADCs) are composed of M conversion stages effectively connected in series, where M is an integer. Such analog-to-digital converters convert samples of an analog input signal to respective N-bit digital values that collectively constitute a digital output signal. Each conversion stage receives an analog signal. The conversion stage comprises a sample-and-hold circuit or a track-and-hold circuit that samples the analog signal to generate an analog signal sample. The conversion stage additionally comprises one or more comparators each of which compares the analog signal sample with a respective threshold to generate a respective bit signal that provides a respective bit of the digital output signal. The conversion stage additionally derives an analog residual signal from the analog signal sample and the bit signal. The first conversion stage receives the analog input signal as its analog signal and generates the most-significant bit or bits of the digital output signal. Each remaining conversion stage receives the analog residual signal generated by the previous conversion stage as its analog signal and generates one or more of the less-significant bits of the digital output signal.
In this disclosure, the term multi-stage analog-to-digital converter will be regarded as encompassing an analog-to-digital converter having M physical conversion stages in series, as described above. The term will additionally be regarded as encompassing an M-stage cyclic analog-to-digital converter having a single conversion stage. Such a cyclic analog-to-digital converter converts the analog input signal to the digital output signal in M consecutive conversion periods. The analog residual signal generated by the conversion stage in one conversion period provides the analog input signal of the conversion stage in the next conversion period.
Multi-stage analog-to-digital converters are subject to metastable states. These occur whenever the level of the analog signal is so close to a threshold of the comparator of one of the conversion stages that the comparator takes a long time to determine the state of the bit signal, i.e., whether to generate the bit signal as a logical 1 or a logical 0. If the metastable state propagates into two or more succeeding circuits, including both the digital signal path to which the bit signal is input and the conversion stages, the metastable state may be resolved as a logical 1 in one circuit, and as a logical 0 in another. Alternatively, the metastable state may be treated as an intermediate value in a succeeding stage. This inconsistency in interpreting the level represented by the analog input signal is what causes metastable states to become metastable errors in the digital output signal generated by the analog-to-digital converter. Metastable errors in the digital output signal are also known as sparkle codes.
The frequency at which metastable errors are tolerable is strongly application dependent. Some communication applications are said to tolerate half-scale metastable error rates as high as 10−4. Instrumentation applications such as oscilloscopes may operate for long times with peak detection operations occurring on the output data. In this case, metastable errors larger than the thermal noise level must seldom occur in the time over which such measurements can be made. This might lead to a maximum allowable metastable error rate of less than 10−17.
ADCs known as flash ADCs turn metastable states into metastable errors when such ADCs propagate a single metastable comparator value into two different paths in the logic that encodes 2N−1 comparator results into an N-bit binary value. Therefore, the metastable error rate of a flash ADC can be reduced by adding pipelining flipflops between each comparator and the binary encoder. For every flipflop with regeneration time constant Tr and with a clock period Ts added, the probability of a metastable error is reduced by exp (Ts/Tr).
In a refinement, the 2N−1 comparator outputs are encoded into N-bit Gray code before the pipelining flipflops. The key characteristic of Gray (and Gray-like) codes is that at each increment of the code value, only one bit changes. This means that if any one comparator is metastable, exactly one Gray-encoded bit will be metastable. The Gray encoder is followed by pipelining flipflops, which resolve the metastable state, and a Gray-to-binary transcoder to generates the binary output.
ADCs known as Folding and Interpolating ADCs can inherently produce a Gray-coded or Gray-like coded digital output signal. Therefore, such ADCs can also take advantage of the above-described technique to reduce metastable errors without the need to provide an additional Gray encoder.
In A 90 nm CMOS 1.2V 6b 1 GS/s Two-step Subranging ADC, ISSCC 2006, PAPER 31.2A, Figuerido et al. describe how an ADC known as a sub-ranging ADC can be made more tolerant of metastable states. In this, two banks of fine comparators are used in a way that prevents a delayed change in a first-stage comparator due to a metastable state from changing the references actually needed for the second stage. However, this technique imposes a cost of 1.5 bits of redundancy, i.e., this technique employs approximately three times as many comparators than a more conventional ADC.
In A 6b 600 MS/s 5.3 mW Asynchronous ADC in 0.13 μm CMOS, ISSCC 2006, PAPER 31.5, Chen et al. (Chen) disclose a successive-approximation ADC that is resistant to metastable states, specifically to metastable states that cause the asynchronous timing circuit take too long to settle. Chen's circuit still requires that a metastable comparator decision be resolved before the circuit can proceed to the next step of the successive approximation.
In general, multi-stage ADCs are more susceptible to metastable errors because, in each stage, such ADCs generate one or more bit signals together with an analog residual signal that provides the analog input signal of the next stage. Any metastable comparator value will eventually resolve itself in the following digital logic, but only a limited time is available for the analog residual signal to be formed before it is sampled by the next stage. Once the analog residual signal has been sampled, a conversion error will occur if the comparator does not eventually resolve to the same state as the one used to form the analog residual signal. This requirement can limit the conversion rate of the ADC.
FIG. 1 is a block diagram showing an example of a conventional one-bit-per-stage analog-to-digital conversion stage 10 suitable for use as one conversion stage of a multi-stage analog-to-digital converter. Conversion stage 10 constitutes part of an analog-to-digital converter (not shown) capable of converting samples of an analog input signal Ain to a digital output signal. Analog input signal Ain is a voltage or a current: the letter A is used generically to denote either. Analog input signal Ain has a level within the input range of the analog-to-digital converter. The input range extends from a negative full-scale level −Afs to a positive full-scale level +Afs.
Conversion stage 10 is composed of a track-and-hold circuit 12, a comparator 14, a digital-to-analog converter 16, a summing element 18 and an amplifier 20.
Track-and-hold circuit 12 has a signal input, a clock input and an output. The signal input of track-and-hold circuit 12 is connected to receive an analog input signal Ain. When conversion stage 10 provides the most-significant bit of the digital signal generated by the analog-to-digital converter of which the conversion stage constitutes part, analog input signal Ain is the analog input signal of the analog-to-digital converter. Otherwise, analog input signal Ain is the analog residual signal generated by the previous conversion stage, i.e., the conversion stage that provides the next-more significant bit of the digital output signal. Alternatively, in a cyclic analog-to-digital converter, analog input signal Ain is the analog residual signal generated by conversion stage 10 in the previous conversion cycle. Track-and-hold circuit 12 tracks analog input signal Ain until a track clock signal TCK received at its clock input changes state. This state of track clock signal TCK sets track-and-hold circuit 12 it its hold mode in which it holds analog input signal Ain until track clock signal TCK reverts to its original state. In its hold mode, track-and-hold circuit 12 provides an analog signal sample As to comparator 14 and summing element 18. The level of analog signal sample As is equal to the instantaneous level of analog input signal Ain at the time at which track clock signal TCK changed track-and-hold circuit to its hold mode.
Comparator 14 has a signal input, a clock input and a bit signal output. The signal input of comparator 14 is connected to the output of track-and-hold circuit 12. The bit signal output of comparator 14 provides the bit signal output of conversion stage 10 at which the conversion stage outputs a respective bit signal Bout. The clock input of comparator 14 is connected to receive a comparator clock signal CCK, which changes state after track clock signal TCK. In response to comparator clock signal CCK, comparator 14 compares analog signal sample As received at its signal input with a threshold. The threshold of comparator 14 is also a voltage or a current, depending on whether analog input signal is a voltage or a current, respectively.
Digital-to-analog converter 16 is a one-bit digital-to-analog converter having a digital input and an analog output. The digital input is connected to receive bit signal Bout from the output of comparator 14. Digital-to-analog converter 16 converts the bit signal Bout received at its digital input to a recovered analog signal Ar. Recovered analog signal Ar is equal to negative one-half of full-scale (−Afs/2) when bit signal Bout is in a first state, e.g., logical zero, and is equal to positive one-half of full scale (−Afs/2) when bit signal Bout is in a second state, e.g., logical one.
Summing element 18 is a two-input summing element having a non-inverting input, an inverting input and an output. The non-inverting input is connected to receive analog signal sample As from the output of track-and-hold circuit 12. The inverting input is connected to receive recovered analog signal Ar from the analog output of digital-to-analog converter 16. Summing element 18 sums analog signal sample As and recovered analog signal Ar to generate an analog combined signal Ac.
Amplifier 20 has an input and an output and, in this example, has a gain nominally equal to two. The input of amplifier 20 is connected to receive analog combined signal Ac from the output of summing element 18. Amplifier 20 amplifies analog combined signal Ac with a gain of two and outputs the analog residual signal Afs of conversion stage 10 at its output.
Operation of conventional conversion stage 10 to convert an analog input signal Ain to bit signal Bout and to provide analog residual signal Ares for input to a following conversion stage (not shown) will now be described with reference to the graphs shown in FIGS. 2A-2E. In the example shown, analog input signal Ain ranges in level from −Afs to +Afs, where Afs indicates full scale of the input range of the analog-to-digital converter.
FIG. 2A is a graph showing the relationship between the level of analog signal sample As at the output of track-and-hold circuit 12 at the time that track clock signal TCK changes state and the level of analog input signal Ain.
FIG. 2B is a graph showing the relationship between the state of bit signal Bout at the output of comparator 14 and the level of analog input signal Ain. In the example shown, the threshold of comparator 14 is zero. Comparator 14 outputs bit signal Bout in a first state, e.g., logical zero, when the level of analog signal sample As is less than its threshold and outputs bit signal Bout in a second state, e.g., logical one, when the level of analog signal sample As is greater than its threshold. As noted above, when the level of analog input signal Ain and, hence, analog signal sample As, differs only slightly from the threshold of comparator 14, comparator 14 may take a substantial time to determine the state of bit signal Bout.
FIG. 2C is a graph showing the relationship between the level of recovered analog signal Ar at the output of digital-to-analog converter 16 and that of analog input signal Ain. For levels of analog input signal Ain less than the threshold of comparator 14, i.e., less than zero in this example, bit signal Bout is in its logical zero state, and the level of recovered analog signal Ar is therefore −Afs/2. On the other hand, for levels of analog input signal Ain greater than the threshold of comparator 14, bit signal Bout is in its logical one state, and the level of recovered analog signal Ar is therefore +Afs/2.
FIG. 2D is a graph showing the relationship between the level of analog combined signal Ac output by summing element 18 and that of analog input signal Ain. For levels of analog input signal Ain less than the threshold of comparator 14, i.e., less than zero in this example, the level of analog combined signal Ac is shifted relative to that of analog input signal Ain by (−(−Afs/2)=+Afs/2) as a result of a recovered analog signal level of −Afs/2 being subtracted from analog signal sample As. For levels of analog input signal Ain greater than the threshold, the level of analog combined signal Ac is shifted relative to that of analog input signal Ain by (−(+Afs/2)=−Afs/2 as a result of a recovered analog signal level of +Afs/2 being subtracted from analog signal sample As. At a level of analog input signal Ain equal to the threshold of comparator 14, the transfer function between analog input signal Ain and combined analog signal Ac exhibits a discontinuity with a substantially infinite slope between levels of −Afs/2 and +Afs/2.
FIG. 2E is a graph showing the relationship between the level of analog residual signal Ares output by amplifier 20 and that of analog input signal Ain. FIG. 2E represents the overall transfer function of conventional conversion stage 10 with respect to analog residual signal Ares. As the level of analog input signal Ain increases from negative full-scale to the threshold of comparator 14, i.e., zero in this example, the level of analog residual signal Ares increases proportionally with a slope of +2 from −Afs to +Afs. Moreover, as the level of analog input signal Ain increases from the threshold of comparator 14 to positive full-scale, the level of analog residual signal Ares again increases proportionally with a slope of +2 from −Afs to +Afs. At a level of analog input signal Ain equal to the threshold of comparator 14, the transfer function between analog input signal Ain and analog residual signal Ares exhibits a discontinuity between levels of −Afs and +Afs with a slope typically limited by the slew rate of amplifier 20.
When the output of comparator 14 is in a metastable state, the level of recovered analog signal Ar output by digital-to-analog converter 16 may be equal to +Afs/2 or to −Afs/2. Alternatively, the level of recovered analog signal Ar may be at an indeterminate level between +Afs/2 and −Afs/2. The output of comparator 14 does not consistently correspond to the final state of bit signal Bout because the state of bit signal Bout is not yet decided. Consequently, when analog residual signal Ares is sampled by the track-and-hold circuit of the following conversion stage (not shown), the metastable state of bit signal Bout must be resolved before the track clock signal of the following conversion stage changes to its hold state. If the metastable state is not resolved, bit signal Bout may resolve to a state inconsistent with analog residual signal Ares that provides the analog input signal Ain of the following conversion stage. In this event, a conversion error will occur.
Accordingly, what is needed is an effective way to prevent conversion errors resulting from metastable states of the comparator of a conversion stage of a multi-stage analog-to-digital converter.